PDP11/40 Memory Map Question

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Forgive the newb question, but in the PDP11 Processor Handbook there's a memory map in Appendix B. In that appendix, 240 says it's 11/45 PIRQ. Meanwhile, over in Unix V6 low.s (low memory for the kernel, It's BRK-5, which I thought was TM. My question is - is the memory map set in stone (ROM) or is it just a suggestion for a typical instance (RAM), or am I way off? V6 also maps 300 and 340, whereas the 11/40 handbook talks about floating starting at 300...

Thanks,

Will

[Johnny Billquist]

Post by ***@gmail.com
Forgive the newb question, but in the PDP11 Processor Handbook there's a memory map in Appendix B. In that appendix, 240 says it's 11/45 PIRQ. Meanwhile, over in Unix V6 low.s (low memory for the kernel, It's BRK-5, which I thought was TM. My question is - is the memory map set in stone (ROM) or is it just a suggestion for a typical instance (RAM), or am I way off? V6 also maps 300 and 340, whereas the 11/40 handbook talks about floating starting at 300...

You are confusing several things.

First of all, what you are talking about are the interrupt and trap
vectors. Some of these are hardwired by the CPU, others are configured
on controllers. Some by dip switches, and some through software.

BR-n is the interrupt priority of any interrupt, and have nothing to do
with what vector it uses. There are only 8 interrupt priorities, and
only four are actually available out on the bus, meaning all controllers
are interrupting on BR-4, BR-5, BR-6 or BR-7.

But in general, almost all controllers are at BR-5. There are a few that
go on a different level, but it's rather unusual. This is important
because in the PSW, you can set at what level the CPU is currently
running, and any interrupts at a lower level are then blocked.

Now, vector 240 is indeed PIRQ, or the program controlled interrupt
request. It's the same as any external device interrupt. The program can
set a bit in the PIRQ register, and the CPU will trap to vector 240, if
the PIRQ level is higher than the PSW level. And in the PIRQ register
you have one bit for each level (so this is basically the only source of
interrupts at BR-1, BR-2 or BR-3).

BR-0 is actually not a level at all, but the normal level the CPU is
running at when any interrupt is allowed. If you actually had something
that generated an interrupt at BR-0, it would never generate an
interrupt, since the CPU cannot be at a lower level (in the PSW) then 0.

Floating space basically means the space where DEC haven't reserved the
vectors for something specific. So it's more a free for all grabbing of
vectors above 300.

Johnny

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Post by Johnny Billquist

Forgive the newb question, but in the PDP11 Processor Handbook there's a memory map in Appendix B. In that appendix, 240 says it's 11/45 PIRQ. Meanwhile, over in Unix V6 low.s (low memory for the kernel, It's BRK-5, which I thought was TM. My question is - is the memory map set in stone (ROM) or is it just a suggestion for a typical instance (RAM), or am I way off? V6 also maps 300 and 340, whereas the 11/40 handbook talks about floating starting at 300...

You are confusing several things.
First of all, what you are talking about are the interrupt and trap
vectors. Some of these are hardwired by the CPU, others are configured
on controllers. Some by dip switches, and some through software.
BR-n is the interrupt priority of any interrupt, and have nothing to do
with what vector it uses. There are only 8 interrupt priorities, and
only four are actually available out on the bus, meaning all controllers
are interrupting on BR-4, BR-5, BR-6 or BR-7.
But in general, almost all controllers are at BR-5. There are a few that
go on a different level, but it's rather unusual. This is important
because in the PSW, you can set at what level the CPU is currently
running, and any interrupts at a lower level are then blocked.
Now, vector 240 is indeed PIRQ, or the program controlled interrupt
request. It's the same as any external device interrupt. The program can
set a bit in the PIRQ register, and the CPU will trap to vector 240, if
the PIRQ level is higher than the PSW level. And in the PIRQ register
you have one bit for each level (so this is basically the only source of
interrupts at BR-1, BR-2 or BR-3).
BR-0 is actually not a level at all, but the normal level the CPU is
running at when any interrupt is allowed. If you actually had something
that generated an interrupt at BR-0, it would never generate an
interrupt, since the CPU cannot be at a lower level (in the PSW) then 0.
Floating space basically means the space where DEC haven't reserved the
vectors for something specific. So it's more a free for all grabbing of
vectors above 300.
Johnny

Great answer. I was totally confused. Gotta start somewhere, though... I watched some very helpful PDP11 instructional videos that cleared up the BR levels stuff. That combined with your answer put me well on my way. Not surprisingly, the v6 code reads (I read it) correctly now :).

Thanks.

Will